1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same and, more particularly, to an improvement of a method of forming an electrode or a wiring layer.
2. Description of the Related Art
In recent years, as the integration density of a semiconductor device has been increased, the thickness and width of a wiring layer have been decreased, and a multi-layered wiring structure has been developed. An Al alloy containing aluminum (Al) as a main component has been conventionally used as a wiring material due to its low wiring resistance and its high workability.
However, even when the sectional area of a wiring layer is decreased, a signal current amount required for the wiring layer is not reduced. For this reason, a current density is increased, and disconnection of the wiring layer disadvantageously occurs due to electro-migration (to be referred to as EM hereinafter). In addition, as a multi-layered wiring is developed, the wiring layer receives complex heat hysteresis. For this reason, disconnection of the wiring layer disadvantageously occurs due to stress migration (to be referred to as SM hereinafter) caused by a thermal stress acting on the wiring layer. In a device, although the high-speed operation and low power consumption of a switching element are strongly demanded, Al cannot easily satisfy the demand because of its material properties.
Noble metals, such as copper (Cu) and silver (Ag), having a resistivity lower than that of Al and a melting point higher than that of Al, have received a great deal of attention and have been examined as next-generation materials.
The electric resistivities, melting points, and self-diffusion coefficients of Al, tungsten (W), Cu, and Ag are shown in Table 1. In this case. the diffusion coefficient D (cm.sup.2 /sec) of a metal is expressed by the following equation: EQU D=D.sub.0 exp (-Q/k.sub.B T)
where k.sub.B represents Boltzman constant, the unit of D.sub.0 is cm.sup.2 /sec, the unit of Q is eV, and the unit of T is K. In Table 1, D.sub.0 and Q are represented.
TABLE 1 ______________________________________ Electric Melting Self-diffusion Resistivity Point Coefficient Element .mu..OMEGA. .multidot. cm .degree.C. D0 (cm.sup.2 /sec) Q (ev) ______________________________________ Al 2.61 660 1.71 1.48 W 5.30 3382 1.90 6.07 Cu 1.72 1083 0.20 2.04 Ag 1.47 960 0.46 1.91 ______________________________________
According to Table 1, the melting point and self-diffusion coefficient of the noble metal, such as Cu or Ag, are more than those of Al, but the resistivity of the noble metal is lower than that of Al. In general, it is known that a wiring material having a high melting point and a large self-diffusion coefficient has excellent EM and SM resistances. The EM resistance is improved for the following reason. The switching speed for the device is determined by the product of the wiring resistance: R and the capacitor: C. That is, since the self-diffusion coefficient of the noble metal, such as Cu or Ag, is sufficiently smaller than that of Al, atomic diffusion in crystal grains and a crystal grain boundary, and on the surfaces of a wiring layer as paths is reduced.
In this manner, the noble metal, such as Cu or Ag, is more excellent than Al in reliability and electric resistivity, and an RC delay caused by a long wiring layer can be relaxed by applying a noble metal wiring layer to a device. For this reason, decrease in switching speed can be suppressed. In addition, power consumption in a wiring portion can be decreased and the reliability of the wiring layer can be improved.
When Cu is used as a wiring material, a metal wiring layer is conventionally formed by the following method. That is, as shown in FIG. 1A, an oxide film 202 is formed on a semiconductor substrate 201 consisting of, e.g., silicon. As shown in FIG. 1B, a Cu film 203 is formed on the oxide film 202 by sputtering. As shown in FIG. 1C, a resist pattern 204 is formed on the Cu film 203 by using a photoresist technique. Finally, the Cu film 203 is patterned by RIE (Reactive Ion Etching) using the resist pattern 204 as a mask so as to form a Cu wiring layer.
However, the method of this type has the following problems.
When a Cu wiring layer is to be formed, since there is no halide having a high vapor pressure at about an atmospheric temperature, RIE must be performed at a high temperature of 300.degree. C. or more. The resist pattern 204 is degraded during etching of the Cu film 203 because the heat resistance of the resist generally is about 200.degree. C. For this reason, as shown in FIG. 1D, a pattern width is decreased or the surface of the wiring layer is deformed, so a Cu wiring layer having a predetermined shape cannot be formed.
A Cu film has no acid-resistance because a passivation film is not formed on Cu unlike on Al film. For this reason, when ashing of the resist pattern 204 is performed by oxygen to remove the resist pattern 204, as shown in FIG. 1E, the surface and inside of a Cu wiring layer 205 are oxidized, and the electric resistivity of the Cu wiring layer 205 is increased. In addition, Cu atoms 206 in the Cu wiring layer 205 are diffused in a deep portion of the oxide film 202 because Cu is diffused in an oxide film at high speed, so that an operation error occurs in the element. The adhesion properties between the wiring layer and an insulating interlayer or a passivation film are disadvantageously degraded.
As a method of solving the problems caused by ashing, a method of forming a so-called buried wiring layer is proposed. According to this method, a groove serving as a wiring layer is formed in the substrate surface, and a wiring material is selectively grown in the groove by CVD.
However, when an organic source is used as a source gas for selective CVD, impurities such as carbon atoms, hydrogen atoms, and oxygen atoms are mixed in the buried wiring layer, and a low resistivity which is the original characteristic of the material cannot be obtained.